Verilog Commands

🔌 Verilog Commands – Module Basics

Topic	Question	Answer
Verilog	Module declaration	module name(input clk, output reg q);
Verilog	Module with parameters	module name #(parameter WIDTH=8) (input [WIDTH-1:0] data);
Verilog	Endmodule	endmodule
Verilog	Input port	input [7:0] data_in
Verilog	Output port	output [7:0] data_out
Verilog	Output reg	output reg [7:0] result
Verilog	Inout port	inout [7:0] bus
Verilog	Port list declaration	module name(clk, rst, data); input clk, rst; ...
Verilog	Wire declaration	wire [7:0] data;
Verilog	Multi-wire	wire a, b, c;
Verilog	Wire with assignment	wire [7:0] result = a + b;
Verilog	Reg declaration	reg [15:0] address;
Verilog	Integer declaration	integer count;
Verilog	Real declaration	real voltage;
Verilog	Time declaration	time current_time;
Verilog	Parameter	parameter WIDTH = 8;
Verilog	Parameter in module	parameter WIDTH = 8, DEPTH = 16;
Verilog	Localparam	localparam DEPTH = 16;
Verilog	Define constant	`define MAX_COUNT 100
Verilog	Include file	`include "filename.v"
Verilog	Ifdef conditional	`ifdef SYNTHESIS ... `endif
Verilog	Ifndef	`ifndef DEBUG ... `endif
Verilog	Else conditional	`ifdef SIM ... `else ... `endif
Verilog	Elsif conditional	`ifdef A ... `elsif B ... `endif
Verilog	Timescale	`timescale 1ns/1ps

🔌 Verilog Commands – Data Types & Operators

Topic	Question	Answer
Verilog	Assign statement	assign out = in1 & in2;
Verilog	Continuous assignment	assign result = a + b;
Verilog	Blocking assignment	data = 8'hFF;
Verilog	Non-blocking assignment	data <= 8'hFF;
Verilog	Binary literal	4'b1010
Verilog	Hex literal	8'hFF
Verilog	Decimal literal	8'd255
Verilog	Octal literal	8'o377
Verilog	Underscore in literal	32'h00FF_00FF
Verilog	Signed literal	8'sd-5
Verilog	Concatenation	{a, b, c}
Verilog	Replication	{4{1'b1}} (creates 4’b1111)
Verilog	Nested concatenation	{a, {2{b}}, c}
Verilog	Bit select	data[3]
Verilog	Part select	data[7:4]
Verilog	Part select variable	data[base +: 4] or data[base -: 4]
Verilog	Bitwise AND	a & b
Verilog	Bitwise OR	a | b
Verilog	Bitwise XOR	a ^ b
Verilog	Bitwise XNOR	a ~^ b or a ^~ b
Verilog	Bitwise NOT	~a
Verilog	Logical AND	a && b
Verilog	Logical OR	a || b
Verilog	Logical NOT	!a
Verilog	Equality	a == b
Verilog	Inequality	a != b
Verilog	Case equality	a === b
Verilog	Case inequality	a !== b
Verilog	Less than	a < b
Verilog	Greater than	a > b
Verilog	Less or equal	a <= b (context-dependent)
Verilog	Greater or equal	a >= b
Verilog	Reduction AND	&data
Verilog	Reduction OR	|data
Verilog	Reduction XOR	^data
Verilog	Shift left	data << 2
Verilog	Shift right	data >> 2
Verilog	Arithmetic shift right	data >>> 2
Verilog	Addition	a + b
Verilog	Subtraction	a - b
Verilog	Multiplication	a * b
Verilog	Division	a / b
Verilog	Modulus	a % b
Verilog	Power	a ** b
Verilog	Conditional operator	condition ? true_val : false_val

🔌 Verilog Commands – Behavioral Constructs

Topic	Question	Answer
Verilog	Always block	always @(posedge clk) begin ... end
Verilog	Always combinational	always @(*) begin ... end
Verilog	Always with reset	always @(posedge clk or negedge rst_n) begin ... end
Verilog	If statement	if (condition) begin ... end
Verilog	If-else	if (cond) begin ... end else begin ... end
Verilog	If-else-if	if (c1) ... else if (c2) ... else ...
Verilog	Case statement	case (expr) val1: ...; val2: ...; default: ...; endcase
Verilog	Casex (don’t care)	casex (data) 4'b1xxx: ...; endcase
Verilog	Casez (high-Z)	casez (data) 4'b1???: ...; endcase
Verilog	For loop	for (i = 0; i < N; i = i + 1) begin ... end
Verilog	While loop	while (condition) begin ... end
Verilog	Repeat loop	repeat (N) begin ... end
Verilog	Forever loop	forever begin ... end
Verilog	Disable statement	disable block_name;
Verilog	Task definition	task name; input x; output y; ... endtask
Verilog	Task with timing	task name; #10; ... endtask
Verilog	Call task	name(arg1, arg2);
Verilog	Function definition	function [7:0] name; input [7:0] x; ... endfunction
Verilog	Function automatic	function automatic [7:0] name(input [7:0] x); ... endfunction
Verilog	Function call	result = name(arg);
Verilog	Begin-end block	begin ... end
Verilog	Named block	begin: block_name ... end
Verilog	Fork-join parallel	fork ... join
Verilog	Parallel block	fork ... join

🔌 Verilog Commands – Structural & Generate

Topic	Question	Answer
Verilog	Module instantiation	module_name inst (.port1(sig1), .port2(sig2));
Verilog	Positional instantiation	module_name inst (sig1, sig2, sig3);
Verilog	Instance with parameters	module_name #(.WIDTH(16)) inst (.clk(clk));
Verilog	Instance array	module_name inst[3:0] (.in(in), .out(out));
Verilog	Generate for	generate for (i=0; i<N; i=i+1) begin ... end endgenerate
Verilog	Generate if	generate if (WIDTH==8) begin ... end endgenerate
Verilog	Generate case	generate case (MODE) ... endcase endgenerate
Verilog	Genvar declaration	genvar i;
Verilog	Generate block name	generate for (i=0; i<N; i=i+1) begin: gen_block ... end endgenerate
Verilog	Specify block	specify ... endspecify
Verilog	Path delay	specify (a => b) = 10; endspecify

🔌 Verilog Commands – Memory & Arrays

Topic	Question	Answer
Verilog	Memory array	reg [7:0] mem [0:255];
Verilog	2D memory	reg [7:0] mem [0:15][0:15];
Verilog	Access memory	data = mem[addr];
Verilog	Write memory	mem[addr] = data;
Verilog	Initialize memory	integer i; initial for (i=0; i<256; i=i+1) mem[i] = 0;
Verilog	Memory size	parameter DEPTH = 256;

🔌 Verilog Commands – Simulation & System Tasks

Topic	Question	Answer
Verilog	Initial block	initial begin ... end
Verilog	Display task	$display("Value = %d", data);
Verilog	Display hex	$display("Hex: %h", data);
Verilog	Display binary	$display("Binary: %b", data);
Verilog	Write (no newline)	$write("Text");
Verilog	Monitor signals	$monitor("time=%0t data=%h", $time, data);
Verilog	Monitor on/off	$monitoron; and $monitoroff;
Verilog	Strobe	$strobe("Value at end: %d", data);
Verilog	Finish simulation	$finish;
Verilog	Finish with code	$finish(2);
Verilog	Stop simulation	$stop;
Verilog	Simulation time	$time
Verilog	Real time	$realtime
Verilog	Scale time	$stime
Verilog	Time format	$timeformat(-9, 2, " ns", 10);
Verilog	Read memory hex	$readmemh("file.hex", memory);
Verilog	Read memory binary	$readmemb("file.bin", memory);
Verilog	Write memory hex	$writememh("file.hex", memory);
Verilog	Write memory binary	$writememb("file.bin", memory);
Verilog	Random number	$random
Verilog	Random with seed	$random(seed)
Verilog	Distribution	$dist_uniform(seed, min, max)
Verilog	Dump file	$dumpfile("wave.vcd");
Verilog	Dump variables	$dumpvars(0, top);
Verilog	Dump on	$dumpon;
Verilog	Dump off	$dumpoff;
Verilog	Dump all	$dumpall;
Verilog	Dump flush	$dumpflush;
Verilog	Dump limit	$dumplimit(size);
Verilog	Fatal error	$fatal(1, "Critical error");
Verilog	Error message	$error("Error occurred");
Verilog	Warning message	$warning("Warning");
Verilog	Info message	$info("Information");

🔌 Verilog Commands – Timing & Events

Topic	Question	Answer
Verilog	Delay	#10; (10 time units)
Verilog	Inter-assignment delay	#10 data = value;
Verilog	Intra-assignment delay	data = #10 value;
Verilog	Wait statement	wait (condition);
Verilog	Event declaration	event event_name;
Verilog	Trigger event	-> event_name;
Verilog	Wait for event	@(event_name);
Verilog	Wait posedge	@(posedge clk);
Verilog	Wait negedge	@(negedge clk);
Verilog	Wait any change	@(a or b or c);
Verilog	Wait any change (shorthand)	@* or @(*)
Verilog	Multiple events	@(posedge clk or negedge rst);