System Verilog Commands

⚡ SystemVerilog Commands – Enhanced Data Types

Topic	Question	Answer
SV	Module declaration	module name(input logic clk, output logic q);
SV	Interface port	interface_name.modport port_name
SV	Always combinational	always_comb begin ... end
SV	Always sequential	always_ff @(posedge clk) begin ... end
SV	Always latch	always_latch begin ... end
SV	Logic declaration	logic [31:0] value;
SV	Logic 2-state	bit [3:0] nibble;
SV	Byte type	byte signed_byte;
SV	Shortint type	shortint data;
SV	Int type	int counter;
SV	Longint type	longint big_num;
SV	Packed array	logic [7:0][3:0] packed_array;
SV	Unpacked array	logic [7:0] unpacked [0:15];
SV	Dynamic array declare	logic [7:0] dyn_array [];
SV	Dynamic array new	dyn_array = new[10];
SV	Dynamic array resize	dyn_array = new[20] (dyn_array);
SV	Dynamic array delete	dyn_array.delete();
SV	Dynamic array size	size = dyn_array.size();
SV	Associative array	logic [7:0] assoc_array [int];
SV	Associative array string	logic [7:0] assoc [string];
SV	Associative exists	if (assoc.exists(key))
SV	Associative delete	assoc.delete(key);
SV	Associative first	assoc.first(key);
SV	Associative next	assoc.next(key);
SV	Associative num	size = assoc.num();
SV	Queue declaration	logic [7:0] queue [$];
SV	Queue with max	logic [7:0] queue [$:15];
SV	Push back	queue.push_back(data);
SV	Push front	queue.push_front(data);
SV	Pop back	data = queue.pop_back();
SV	Pop front	data = queue.pop_front();
SV	Queue insert	queue.insert(index, data);
SV	Queue delete	queue.delete(index);
SV	Queue size	size = queue.size();
SV	Array default	int a[10] = '{default:5};
SV	Array literal	int a[3] = '{1, 2, 3};
SV	Array pattern	int a[4] = '{0:1, 1:2, default:0};
SV	Assign all bits 1	bit [31:0] data = '1;
SV	Assign all bits 0	bit [31:0] data = '0;
SV	Streaming operator	{>>byte_data} = stream;
SV	Typedef enum	typedef enum {IDLE, RUN, DONE} state_t;
SV	Enum with values	typedef enum {RED=1, GREEN=2, BLUE=4} color_t;
SV	Enum first	color_t c = c.first();
SV	Enum next	c = c.next();
SV	Enum name	string name = c.name();
SV	Typedef struct	typedef struct {int x; int y;} point_t;
SV	Packed struct	typedef struct packed {bit[3:0] a; bit[3:0] b;} data_t;
SV	Union	typedef union {int i; real r;} union_t;
SV	Tagged union	typedef union tagged {int i; real r;} tagged_u;

⚡ SystemVerilog Commands – Interfaces & Modports

Topic	Question	Answer
SV	Interface declaration	interface name; logic [7:0] data; endinterface
SV	Interface with parameter	interface name #(parameter WIDTH=8); ...
SV	Modport master	modport master (input data_in, output data_out);
SV	Modport slave	modport slave (output data_in, input data_out);
SV	Clocking block	clocking cb @(posedge clk); input data; endclocking
SV	Modport with clocking	modport tb (clocking cb);
SV	Interface instantiation	interface_name inst();
SV	Connect interface	module_name dut(.bus(inst.master));
SV	Virtual interface	virtual interface_name vif;
SV	Assign virtual interface	vif = inst;

⚡ SystemVerilog Commands – Classes & OOP

Topic	Question	Answer
SV	Class declaration	class name; int var; function new(); endfunction; endclass
SV	Class with parameter	class name #(parameter WIDTH=8); ...
SV	Class constructor	function new(); var = 0; endfunction
SV	Constructor with args	function new(int init_val); var = init_val; endfunction
SV	Create object	name obj = new();
SV	Create with args	name obj = new(10);
SV	Class property	int data;
SV	Local property	local int private_data;
SV	Protected property	protected int prot_data;
SV	Static property	static int shared_count;
SV	Const property	const int SIZE = 10;
SV	Class method	function void display(); ... endfunction
SV	Task in class	task run(); ... endtask
SV	Static method	static function int get_count(); ... endfunction
SV	Extern method	extern function void compute();
SV	Virtual method	virtual function void process(); ... endfunction
SV	Class inheritance	class child extends parent; ... endclass
SV	Super call	super.method();
SV	Super new	function new(); super.new(); endfunction
SV	This keyword	this.var = value;
SV	Abstract class	virtual class name; pure virtual function void f(); endclass
SV	Polymorphism	parent p = child::new();
SV	Copy object	dest = src.copy();
SV	Clone object	new_obj = obj.clone();
SV	Compare objects	if (obj1.compare(obj2))

⚡ SystemVerilog Commands – Constraints & Randomization

Topic	Question	Answer
SV	Rand variable	rand int data;
SV	Randc variable	randc bit [3:0] value;
SV	Constraint block	constraint c_name { x > 0; x < 100; }
SV	Constraint range	constraint c { x inside {[1:10]}; }
SV	Constraint distribution	constraint c { x dist {0:=40, [1:3]:=60}; }
SV	Constraint implication	constraint c { if (mode == 0) x < 10; }
SV	Constraint foreach	constraint c { foreach (arr[i]) arr[i] < 100; }
SV	Soft constraint	constraint c { soft x == 5; }
SV	Constraint disable	obj.c_name.constraint_mode(0);
SV	Constraint enable	obj.c_name.constraint_mode(1);
SV	Randomize	if (!randomize()) $error("Failed");
SV	Randomize variable	if (!obj.randomize())
SV	Randomize with	randomize(x) with { x > 10; x < 20; };
SV	Pre-randomize	function void pre_randomize(); ... endfunction
SV	Post-randomize	function void post_randomize(); ... endfunction
SV	Disable rand	rand_mode(0);
SV	$urandom	data = $urandom();
SV	$urandom_range	data = $urandom_range(min, max);

⚡ SystemVerilog Commands – Assertions

Topic	Question	Answer
SV	Immediate assert	assert (condition) else $error("Failed");
SV	Immediate assert no action	assert (a == b);
SV	Assume statement	assume (condition);
SV	Cover statement	cover (condition);
SV	Assert property	assert property (@(posedge clk) req |-> ack);
SV	Assume property	assume property (@(posedge clk) req |-> ack);
SV	Cover property	cover property (@(posedge clk) req ##1 ack);
SV	Sequence definition	sequence seq; @(posedge clk) a ##1 b; endsequence
SV	Sequence delay	sequence seq; a ##2 b; endsequence
SV	Sequence range delay	sequence seq; a ##[1:3] b; endsequence
SV	Sequence repetition	sequence seq; a[*3]; endsequence
SV	Sequence goto repetition	sequence seq; a[->3]; endsequence
SV	Sequence non-consecutive	sequence seq; a[=3]; endsequence
SV	Sequence throughout	sequence seq; a throughout b[*3]; endsequence
SV	Property definition	property prop; @(posedge clk) a |-> ##[1:3] b; endproperty
SV	Property implication	property prop; req |-> ack; endproperty
SV	Property if-else	property prop; if (mode) (a |-> b) else (c |-> d); endproperty
SV	Property disable iff	property prop; @(posedge clk) disable iff (rst) req |-> ack; endproperty
SV	Concurrent assert	assert_name: assert property (prop) else $error("Failed");
SV	Assertion with action	assert property (prop) pass_action else fail_action;

⚡ SystemVerilog Commands – Processes & IPC

Topic	Question	Answer
SV	Fork-join	fork ... join
SV	Fork-join_any	fork ... join_any
SV	Fork-join_none	fork ... join_none
SV	Wait fork	wait fork;
SV	Disable fork	disable fork;
SV	Process control	process p = process::self();
SV	Process await	p.await();
SV	Process kill	p.kill();
SV	Mailbox declaration	mailbox #(int) mbx = new();
SV	Mailbox bounded	mailbox #(int) mbx = new(10);
SV	Mailbox put	mbx.put(data);
SV	Mailbox get	mbx.get(data);
SV	Mailbox try_put	if (mbx.try_put(data))
SV	Mailbox try_get	if (mbx.try_get(data))
SV	Mailbox peek	mbx.peek(data);
SV	Mailbox num	size = mbx.num();
SV	Semaphore declaration	semaphore sem = new(1);
SV	Semaphore get	sem.get(1);
SV	Semaphore put	sem.put(1);
SV	Semaphore try_get	if (sem.try_get(1))
SV	Event declaration	event evt;
SV	Trigger event	-> evt;
SV	Wait event	@evt;
SV	Wait event triggered	wait(evt.triggered);

⚡ SystemVerilog Commands – Packages & Program

Topic	Question	Answer
SV	Package declaration	package pkg_name; ... endpackage
SV	Import package	import pkg_name::*;
SV	Import specific	import pkg_name::item;
SV	Export from package	export pkg_name::item;
SV	Program block	program test; ... endprogram
SV	Initial in program	initial begin ... end
SV	Final block	final begin ... end
SV	$unit scope	Access to compilation-unit scope

⚡ SystemVerilog Commands – Functional Coverage

Topic	Question	Answer
SV	Covergroup definition	covergroup cg @(posedge clk); ... endgroup
SV	Coverpoint	coverpoint data;
SV	Coverpoint with bins	coverpoint data { bins low = {[0:31]}; }
SV	Auto bins	coverpoint data { bins auto[4] = {[0:255]}; }
SV	Illegal bins	illegal_bins bad = {127};
SV	Ignore bins	ignore_bins ign = {255};
SV	Cross coverage	cross addr, data;
SV	Covergroup options	option.per_instance = 1;
SV	Covergroup sample	cg.sample();
SV	Get coverage	real cov = cg.get_coverage();