FPGA Constraints

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Example of PYNQ-Z2 XDC Constraint File

Table of Contents

  1. Introduction to XDC Files
  2. Understanding Your Constraint File
  3. How to Write XDC Constraint Files
  4. PYNQ-Z2 Board Specifications
  5. Best Practices

Introduction to XDC Files

XDC (Xilinx Design Constraints) files are configuration files used in Xilinx FPGA designs to specify:

  • Physical pin assignments (which FPGA pins connect to which board components)
  • Electrical properties (voltage levels, I/O standards)
  • Timing constraints (clock definitions, timing requirements)
  • Configuration settings (bitstream generation options)

These files bridge the gap between your RTL design (Verilog/VHDL) and the physical FPGA hardware.

Understanding Your Constraint File

Let’s break down your pynq_z2_correct.xdc file section by section:

1. Header and Device Information

## PYNQ-Z2 Board Constraint File for Half-Adder
## Device: xc7z020clg400-1 (CORRECT for PYNQ-Z2)
  • Purpose: Documents the target board and FPGA device
  • Device Code Breakdown:
    • xc7z020 = Zynq-7000 series, specific part number
    • clg400 = Package type (CLG = Chip Land Grid, 400 = pin count)
    • -1 = Speed grade (higher numbers = faster, but more power)

2. Pin Assignments

## Input: a (Switch 0)
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {a}]

Syntax Breakdown:

  • set_property: Tcl command to assign properties
  • -dict: Specifies a dictionary of property-value pairs
  • PACKAGE_PIN M20: Physical pin location on the FPGA package
  • IOSTANDARD LVCMOS33: I/O voltage standard (3.3V CMOS logic)
  • [get_ports {a}]: References the port named a in your RTL module

Your Pin Mappings:

RTL PortBoard ComponentPhysical PinI/O Standard
aSwitch 0 (SW0)M20LVCMOS33
bSwitch 1 (SW1)M19LVCMOS33
sumLED 0 (LD0)R14LVCMOS33
carryLED 1 (LD1)P14LVCMOS33

3. Configuration Settings

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

What Each Setting Does:

  1. CFGBVS VCCO: Configuration Bank Voltage Select
    • VCCO means configuration voltage comes from VCCO supply
    • Required for proper FPGA configuration during power-up
  2. CONFIG_VOLTAGE 3.3: Configuration voltage level
    • Specifies 3.3V configuration bank voltage
    • Must match your board’s actual voltage
  3. BITSTREAM.GENERAL.COMPRESS TRUE: Bitstream compression
    • Reduces bitstream file size
    • Faster download times to FPGA
    • No performance penalty after configuration

How to Write XDC Constraint Files

Step-by-Step Guide

Step 1: Identify Your Design Ports

Look at your RTL module definition:

module half_adder (
    input  a,
    input  b,
    output sum,
    output carry
);

Every port needs a constraint (unless it’s internally connected).

Step 2: Find Physical Pin Locations

Consult your board’s documentation:

  • PYNQ-Z2 Reference Manual or Master XDC file
  • Schematic diagrams
  • Pin mapping tables

For PYNQ-Z2, switches and LEDs are pre-wired to specific pins.

Step 3: Determine I/O Standards

Common I/O standards:

  • LVCMOS33: 3.3V CMOS (most common for boards)
  • LVCMOS18: 1.8V CMOS
  • LVDS: Low-Voltage Differential Signaling
  • SSTL15: DDR3 memory interface

Match the voltage level of your board’s components.

Step 4: Write the Constraints

Basic syntax:

set_property -dict {PACKAGE_PIN <pin> IOSTANDARD <standard>} [get_ports {<port_name>}]

Step 5: Add Configuration Settings

For Zynq-7000 devices, always include:

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

Step 6: Optional – Add Timing Constraints

For clocked designs:

## Clock constraint (100 MHz example)
create_clock -period 10.000 -name sys_clk [get_ports clk]

General Syntax Reference

## Single property assignment
set_property PACKAGE_PIN R14 [get_ports {sum}]
set_property IOSTANDARD LVCMOS33 [get_ports {sum}]

## Multiple properties with -dict (preferred)
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {sum}]

## Bus notation
set_property PACKAGE_PIN M20 [get_ports {data[0]}]
set_property PACKAGE_PIN M19 [get_ports {data[1]}]

## Wildcard for multiple ports
set_property IOSTANDARD LVCMOS33 [get_ports {led*}]

PYNQ-Z2 Board Specifications

Device Details

  • FPGA: Xilinx Zynq XC7Z020-1CLG400C
  • Architecture: Dual-core ARM Cortex-A9 + FPGA fabric
  • Logic Cells: 85K
  • Block RAM: 4.9 Mb
  • DSP Slices: 220

Available I/O Components

Switches (Inputs)

ComponentPin LocationSuggested Use
SW0M20Input/Control
SW1M19Input/Control

LEDs (Outputs)

ComponentPin LocationColor
LD0R14Green
LD1P14Green
LD2N16Green
LD3M14Green

Buttons (Inputs)

ComponentPin LocationNote
BTN0D19Active high
BTN1D20Active high
BTN2L20Active high
BTN3L19Active high

RGB LEDs

LEDPin (Red)Pin (Green)Pin (Blue)
LD4N15G17L15
LD5M15L14G14

Note: All general-purpose I/O uses LVCMOS33 standard (3.3V).

Best Practices

1. Organization

  • Group related constraints together
  • Use clear, consistent commenting
  • Include a summary section at the end

2. Naming Conventions

  • Match port names exactly to your RTL
  • Use descriptive names that reflect function
  • Consider hierarchical naming for large designs

3. Comments

## Good: Descriptive comment
## Input: a (Switch 0)
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {a}]

## Better: Include functional description
## Input: a - First operand from Switch 0 (active high)
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {a}]

4. Validation

  • Always check for typos in port names
  • Verify pin locations against board documentation
  • Test on hardware to confirm correct operation

5. Version Control

  • Include device/board information in header
  • Document any deviations from standard configurations
  • Note the date and purpose of modifications

6. Reusability

Create a master constraint file for your board with all available pins, then copy/modify for specific projects.

Example: Expanding Your Design

If you wanted to add more functionality, here’s how you’d expand the constraints:

Adding a Reset Button

## Input: reset (Button 0)
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {reset}]

Adding a Clock

## System Clock (125 MHz oscillator)
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {clk}]
create_clock -period 8.000 -name sys_clk [get_ports {clk}]

Adding More LEDs

## Output: result[2] (LED 2)
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {result[2]}]

## Output: result[3] (LED 3)
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {result[3]}]

Common Errors and Solutions

Error: “Cannot find port ‘xyz'”

  • Cause: Port name in XDC doesn’t match RTL
  • Solution: Check spelling and case sensitivity

Error: “CFGBVS value not specified”

  • Cause: Missing configuration voltage settings
  • Solution: Add CFGBVS and CONFIG_VOLTAGE properties

Warning: “Unconstrained logical port”

  • Cause: RTL port has no physical pin assignment
  • Solution: Add constraint or verify port is intentionally internal

Physical Issues: LED always on/off

  • Cause: Incorrect pin assignment or polarity
  • Solution: Verify pin location and check if active high/low

Quick Reference Template

## ==========================================
## [Board Name] Constraint File
## Device: [device-package-speed]
## Project: [project name]
## Date: [date]
## ==========================================

## Inputs
set_property -dict {PACKAGE_PIN [pin] IOSTANDARD [standard]} [get_ports {input_name}]

## Outputs
set_property -dict {PACKAGE_PIN [pin] IOSTANDARD [standard]} [get_ports {output_name}]

## Clocks (if applicable)
set_property -dict {PACKAGE_PIN [pin] IOSTANDARD [standard]} [get_ports {clk}]
create_clock -period [ns] -name [clk_name] [get_ports {clk}]

## Configuration
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

Additional Resources

  1. Xilinx Documentation:
    • UG835: Vivado Design Suite Tcl Command Reference
    • UG903: Using Constraints
    • UG625: Xilinx Constraints Guide
  2. PYNQ-Z2 Resources:
    • PYNQ-Z2 Reference Manual
    • Board schematic files
    • Master XDC template file
  3. Online Communities:
    • Xilinx Community Forums
    • PYNQ Community Forums
    • Stack Overflow (tags: fpga, xilinx, vivado)

Summary

Your constraint file is well-structured and complete for the half-adder design. It correctly:

  • ✅ Maps inputs to switches
  • ✅ Maps outputs to LEDs
  • ✅ Uses correct pin locations for PYNQ-Z2
  • ✅ Specifies appropriate I/O standard (LVCMOS33)
  • ✅ Includes necessary configuration settings
  • ✅ Is well-documented with clear comments

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