100 Tricky Questions for VLSI Company Interviews
📚 Document Structure
This comprehensive collection contains 100 expert-level interview questions split across 4 parts, covering topics asked by top VLSI companies including Intel, AMD, Nvidia, Qualcomm, ARM, Synopsys, Cadence, and more.
📖 Part 1: Foundation & Core Concepts (Questions 1-25)
File: sv_verilog_interview_questions_part1
Key Topics:
- Data Type Overflow: Q1 (byte infinite loop), Q6 (logic 4-bit overflow)
- Type Mixing: Q2 (bit vs logic with X), Q3 (signed vs unsigned)
- Arrays: Q4, Q7, Q8, Q10, Q11
- Assignments: Q5 (blocking vs non-blocking), Q13 (race conditions)
- X/Z Handling: Q14 (case with X), Q25 (arithmetic propagation)
- OOP Basics: Q18 (virtual functions), Q20 (shallow copy)
- Constraints: Q12, Q22
- SV Features: Q9, Q15, Q16, Q17, Q19, Q21, Q23, Q24
Company Focus: All levels, foundational knowledge
📖 Part 2: Advanced Scenarios & Edge Cases (Questions 26-50)
File: sv_verilog_interview_questions_part2
Key Topics:
- Type Conversion: Q26 (signed/unsigned mixing), Q33 (wildcard ==?)
- Collection Edges: Q27 (empty queue), Q35 (assoc array order), Q38 (foreach 2D)
- Operators: Q28 (ternary with X), Q29 (pre/post increment), Q47 ($urandom_range)
- Control Flow: Q31 (unique case), Q37 (priority if)
- Randomization: Q32 (failure), Q40 (solve-before)
- Functions: Q34 (side effects), Q36 (static variables)
- Timing: Q39 (clocking blocks), Q41 (disable fork), Q44 (events)
- Structures: Q42 (packed struct), Q45 (constructors), Q50 (modports)
- IPC: Q43 (mailbox)
Company Focus: Mid to Senior roles, edge case handling
📖 Part 3: Expert-Level Mastery (Questions 51-75)
File: sv_verilog_interview_questions_part3
Key Topics:
- NBA Pipelines: Q51 (race conditions), Q57 (wait fork)
- Collections Advanced: Q52 (foreach assoc), Q56 (array reduction), Q58 (streaming)
- Enum/Typedef: Q53 (undefined enum values)
- Scope: Q54 (parameter vs localparam), Q55 (package variables)
- Distribution: Q59 (constraint weights := vs 😕)
- Bit Operations: Q60 (bit select variants), Q67 (concatenation)
- OOP Advanced: Q61-Q64, Q71-Q72
- Generate: Q65 (conditional generate)
- Ports: Q66 (inout bidirectional)
- Assertions: Q68, Q70
- Semaphores: Q69
- Coverage: Q73 (cross coverage), Q96 (overflow)
- Execution: Q74 (initial block order), Q75 (unique0 vs unique vs priority)
Company Focus: Senior/Staff roles, deep expertise
📖 Part 4: UVM & Industry Best Practices (Questions 76-100)
File: sv_verilog_interview_questions_part4
Key Topics:
- UVM Factory: Q76 (type vs instance override), Q97 (parameterized transactions)
- Config DB: Q77 (timing), Q85 (vs resource_db), Q88 (vif timing), Q94 (plusargs)
- Sequences: Q78 (item reuse), Q79 (virtual seq), Q81 (priority), Q86 (lock/unlock), Q93 (responses)
- TLM: Q80 (analysis fanout), Q89 (scoreboard exports), Q98 (get/put blocking)
- Phases: Q82 (objections), Q95 (phase jumping)
- Callbacks: Q83 (execution order)
- Field Macros: Q84 (array support), Q87 (flags)
- Constraints: Q90 (inside operator), Q92 (solver limits)
- Reporting: Q91 (report catchers)
- Coverage: Q96 (bin overflow)
- Register Models: Q99 (access modes)
- Watchdog: Q100 (heartbeat)
Company Focus: Verification specialist roles, UVM expertise
🏢 Questions by VLSI Company
Intel / AMD / Nvidia
Q1, Q3, Q6, Q13, Q15, Q26, Q51, Q54, Q76, Q84, Q90, Q96
- CPU/GPU verification focus
- Timing and race conditions
- Factory patterns
- Coverage-driven verification
Qualcomm / Broadcom
Q12, Q22, Q40, Q77, Q78, Q81, Q86, Q92, Q99
- Protocol verification
- Sequence hierarchies
- Constrained-random
- Register models
ARM / Apple
Q18, Q20, Q64, Q72, Q83, Q87, Q93, Q97
- Processor IP verification
- Parameterized VIPs
- Callbacks and flexibility
- Reusable components
Synopsys / Cadence / Mentor
Q76, Q79, Q85, Q88, Q91, Q94, Q95, Q100
- EDA tools and VIP
- UVM best practices
- Advanced features
- Configuration management
Texas Instruments / NXP
Q5, Q13, Q39, Q66, Q68, Q70, Q81
- Mixed-signal interfaces
- Timing synchronization
- Assertion-based verification
- Automotive safety
Xilinx / Altera (Intel FPGA)
Q15, Q19, Q54, Q65, Q82
- FPGA verification
- Parameterization
- Generate constructs
- Phase management